Hae-Seung “Harry” Lee, Ph.D.

Co-founder, Chief Technologist. Professor (MIT). IEEE Fellow.

ATSP Professor of Electrical Engineering and Computer Science, Massachusetts Institute of Technology

Hae-Seung (Harry) Lee is the Founder and Chief Technologist at Omni Design Technologies where he has been since founding the company in 2015. In this role, Harry is responsible for technology development and intellectual property.

Harry received the B.S. and the M.S. degrees in Electronic Engineering from Seoul National University, Seoul, Korea, in 1978 and 1980 respectively. He received the Ph.D. degree in electrical engineering from the University of California, Berkeley, in 1984, where he developed self-calibration techniques for A/D converters. In 2007, Harry Lee co-founded Cambridge Analog Technologies (CAT), Inc. along with Kush Gulati.

Since 1984, he has been on the faculty in the Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, where he is now Professor and the Director of Center for Integrated Circuits and Systems. He has acted as Consultant to Maxim Integrated, Analog Devices, Inc. and MIT Lincoln Laboratories. He has served on the Technology Advisory Committee for Samsung Electronics, Cypress Semiconductor, and Sensata Technologies.  Besides CAT, Inc., he also co-founded SMaL Camera Technologies, Inc in 1999.

His research interests are in the areas of analog integrated circuits with emphasis on analog-to-digital converters in scaled CMOS technologies. Harry is a recipient of the 1988 Presidential Young Investigators’ Award, and a co-recipient ISSCC Jack Kilby Outstanding Student Paper Award in 2002 and 2006. He has served on a number of technical program committees for various IEEE conferences, including the International Electron Devices Meeting, the International Solid-State Circuits Conference, the Custom Integrated Circuits Conference, and the IEEE Symposium on VLSI circuits. Prof. Lee is a Fellow of the IEEE.

U.S. Patents ​

  1. H.-S. Lee, “Differential Switched Capacitor Circuit Having Voltage Amplifiers, and Associated Methods,” allowed, January, 2017
  2. H.-S. Lee, S. Lee, and A. Chandrakasan, “Methods and Apparatus for Reducing Timing-Skew Errors in Time-Interleaved Analog-to-Digital Converters,” U.S. Patent 9,608,652, March. 2017
  3. M. Straayer, H.-S. Lee, et. al., 2-phase threshold detector based circuits, U.S. Patent 9,413,228, Aug. 2016
  4. H.-S. Lee, Buffer amplifier circuit, U.S. Patent 9,356,565, May 2016
  5. H.-S. Lee and S.-H. Lee, Level-crossing based circuit and method with offset voltage cancellation, U.S. Patent 9,252,658, Feb. 2016
  6. H.-S. Lee, Switched capacitor circuits having level-shifting buffer amplifiers, and associated methods, U.S. Patent 9,214,912, Dec. 2015
  7. H.-S. Lee, Buffer amplifier circuit, U.S. Patent 9,154,089, Oct. 2015
  8. H.-S. Lee, Passive offset and overshoot cancellation for sampled-data circuits, U.S. Patent 8,912,838, Dec. 2014
  9. H.-S. Lee, Constant slope ramp circuits for sampled-data circuits, U.S. Patent, 8,854,092, October, 2014
  10. S. Shin, D.-Y. Chang, M. Straayer, and H.-S. Lee, Multi-step ADC with sub-ADC calibration, U.S. Patent, 8,723,706, May 2014
  11. H.-S. Lee, Passive offset and overshoot cancellation for sampled-data circuits, U.S. Patent, 8,643,424, Feb. 2014
  12. M. Straayer, and H.-S. Lee, System and method for background calibration of time interleaved analog to digital converters, U.S. Patent, 8,519,875, August, 2013
  13. H.-S. Lee, Offset cancellation for sampled-data circuits, U.S. Patent, 8,519,769, August, 2013
  14. M. Guytton and H.-S. Lee, 2-phase threshold detector based circuits, U.S. Patent, 8,432,192, April 2013
  15. H.-S. Lee, Offset cancellation for sampled-data circuits, U.S. Patent, 8,373,489, Feb. 2013
  16. H.-S. Lee, Passive offset and overshoot cancellation for sampled-data circuits, U.S. Patent, 8,305,131, Nov. 2012
  17. H.-S. Lee, Constant slope ramp circuits for sampled-data circuits, U.S. Patent, 8,294,495, Oct. 2012
  18. H.-S. Lee, Offset cancellation for sampled-data circuits, U.S. Patent, 7,843,233, Nov. 2010*
  19. H.-S. Lee, Constant slope ramp circuits for sample-data circuits, U.S. Patent, 7,737,732, June 2010*
  20. H.-S. Lee, Reference circuits for sampled-data circuits, U.S. Patent, 7,616,145, Nov. 2009*
  21. H.-S. Lee, and K.G. Fife, Active pixel image sensor with selectable source follower and common source amplifier modes, U.S. Patent, 7,289,149, May  2010
  22. H.-S. Lee, and K.G. Fife, Active pixel image sensor with low noise reset, U.S. Patent, 7,697,050, April  2010
  23. H.-S. Lee, and K.G. Fife, Low noise active pixel image sensor using a modified reset value, U.S. Patent, 7,609,303, Oct. 2009
  24. Matthew Guyton and H.-S. Lee, Low-voltage comparator-based switched-capacitor networks, U.S. Patent, 7,564,273, July 2009
  25. H.-S. Lee, and K.G. Fife, Active pixel image sensor with common gate amplifier, U.S. Patent, 7,557,334, July 2009
  26. H.-S. Lee, Precision sampling circuit, U.S. Patent, 7,532,042, May. 2009*
  27. H.-S. Lee, Reference circuits for sampled-data circuits, U.S. Patent, 7,522,086, April 2009*
  28. H.-S. Lee, Output hold circuits for sample-data circuits, U.S. Patent, 7,504,866, March 2009*
  29. H.-S. Lee, K.G. Fife, L.G. Brooks, and J. Yang, CMOS active pixel with hard and soft reset, U.S. Patent, 7,489,355, Feb. 2009
  30. H.-S. Lee, K.G. Fife, L.G. Brooks, and J. Yang, CMOS active pixel with hard and soft reset, U.S. Patent, 7,489,354, Feb. 2009
  31. H.-S. Lee, Sampled-data circuits using zero crossing detection, U.S. Patent, 7,486,115, Feb. 2009*
  32. H.-S. Lee, Sampled-data circuits using zero crossing detection, U.S. Patent, 7,459,942, Dec. 2008*
  33. H.-S. Lee, and K.G. Fife, Active pixel image sensor with common gate amplifier mode, U.S. Patent, 7,459,667, Dec. 2008
  34. H.-S. Lee, K.G. Fife, L.G. Brooks, and J. Yang, CMOS active pixel with hard and soft reset, U.S. Patent, 7,446,805, Nov. 2008
  35. H.-S. Lee, and K.G. Fife, and L.G. Brooks, Precise CMOS imager transfer function control for expanded dynamic range imaging using variable-height multiple reset pulses, U.S. Patent, 7,417,678, Aug. 2008
  36. J.K. Fiorenza, T. Sepke, H.-S. Lee, and C.G. Sodini, Comparator-based switched capacitor circuit for scaled semiconductor fabrication processes, U.S. Patent, 7,319,425, Jan. 2008**
  37. H.-S. Lee, and K.G. Fife, Operational transconductance amplifier for high-speed, low-power imaging applications, U.S. Patent, 7,289,149, Oct. 2007
  38. H.-S. Lee, Pixel design including in-pixel correlated double sampling circuit, U.S. Patent, 7,277,129, Oct. 2007
  39. H.-S. Lee, Constant slope ramp circuits for sample-data circuits, U.S. Patent, 7,253,600, Aug. 2007*
  40. H.-S. Lee and K. G. Fife, Method for cancellation of the effect of charge feedthrough on CMOS pixel output, U.S. Patent, 7,242,429, July 2007
  41. K. Gulati and H.-S. Lee, Analog-to-digital converter having parametric configurability, U.S. Patent 7,002,501, February 2006
  42. H.-S. Lee and K. G Fife, Circuit and method for cancellation of column pattern noise in CMOS imagers, U.S. Patent 6,903,670,  June 2005
  43. H.-S. Lee and K. G. Fife, CMOS pixel design for minimization of defect-induced leakage current, U.S. Patent 6,881,992, April 2005
  44. K. Gulati and H.-S. Lee, Reconfigurable analog-to-digital converter, U.S. Patent 6,864,822,  March 2005
  45. H.-S. Lee, CMOS active pixel with reset noise reduction, U.S. Patent 6,777,660, August 2004
  46. K. Gulati and H.-S Lee, Reconfigurable analog-to-digital converter, U.S. Patent 6,686,860, February 2003
  47. H.-S. Lee, C. G. Sodini, and K.G Fife, Precise MOS imager transfer function control for expanded dynamic range imaging, U.S. Patent 6,600,471, July 2003
  48. L. Lynn, P. Ferguson, and H.-S. Lee, Capacitor-based digital-to-analog converter with continuous time output, U.S. Patent 6,271,784, August 2001
  49. H.-S. Lee, J. Bulzacchelli, Bandpass sigma-delta modulator employing high-Q resonator for narrowband noise suppression, U.S. Patent 6,157,329, December 2000
  50. H.-S. Lee and A. Shabra, Oversampled pipeline A/D converter with mismatch shaping, U.S. Patent 6,137,431, October 2000
  51. H.-S. Lee, Algorithmic A/D converter with digitally calibrated output, U.S. Patent 5,510,789, April 1996
  52. A. N. Karanicolas and H.-S. Lee, Digitally self-calibrating pipeline analog-to-digital converter, U.S. Patent 5,499,027, March 1996
  53. H.-S. Lee and P. C. Yu, Gain enhancement for amplifier using a replica amplifier, U.S. Patent 5,434,538, July 1995
  54. H.-S. Lee,  Analog-to-digital conversion circuit with improved differential linearity, U.S. Patent 5,416,485, May 1995**
  55. S. Decker, J. L. Wyatt, and H.-S. Lee Resistive fuse circuits for image segmentation and smoothing, U.S. Patent 5,223,754, June 1993
  56. H.- S. Lee, Vehicle safety system for driver pedal misapplication, U.S. Patent 5,193,640,  March 1993
  57. K.K. O, H.-S. Lee and L. R. Reif, Merged bipolar and insulated gate transistors, U.S. Patent 5,028,977, July 1991
  58. H.-S. Lee, J. T. Kung, and R. T. Howe, Digital technique for precise measurement of variable capacitance, U.S. Patent 4,860,232, August 1989

Publications in Refereed Journals

  1. Lee, H.-S. and D. A. Hodges, “Self-Calibration Technique for A/D Converters,” IEEE Trans. Circuits System,  CAS-30, pp. 118-190, March 1983.
  2. Lee, H.-S. and D. A. Hodges, “A Precision Measurement Technique for Residual Polarization in Integrated Circuit Capacitors,”  IEEE Electron Devices Lett.  EDL-5, pp. 417-420, October 1984.
  3. Lee, H.-S., D. A. Hodges, and P. R. Gray, “A Self-Calibrating 15 Bit CMOS A/D Converter,” IEEE J. Solid-State Circuits, SC-19, pp. 813-819, December 1984.
  4. Doernberg, J.,  H.-S. Lee, and D. A. Hodges, “Full-Speed Testing of A/D Converters,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 820-827, December 1984.
  5. Lee, H.-S.  and D. A. Hodges, “Accuracy Considerations in Self Calibrating A/D Converters,” IEEE Trans. Circuits Syst., vol. CAS-32, June 1985.
  6. McCarroll, B. J., C. G. Sodini, and H.-S. Lee, “A  High-Speed CMOS Comparator for Use in an ADC,” IEEE J. Solid-State Circuits, SC-23, pp. 159-165, February 1988.*
  7. Kung, J. T., H.-S. Lee, and R. T. Howe, “A Digital Readout Technique for Capacitive Sensor Applications,” IEEE J. Solid-State Circuits, SC-23, pp. 972-977, August 1988.*
  8. O, K. K., H.-S. Lee, L. R. Reif, and W. Frank, “A 2mm BiCMOS Process Utilizing Selective Epitaxy,” IEEE Electron Device Letters, vol. EDL-9, pp. 567-569, November 1988.*
  9. Tewksbury, T., H.-S. Lee and G. A. Miller, “The Effects of Oxide Traps on the Large-Signal Transient Response of MOS Circuits,” IEEE J. Solid-State Circuits, vol. SC-24, pp. 542-544, April 1989.*
  10. O, K. K., H.-S. Lee, L. R. Reif and W. Frank, “A Shallow Buried Layer Formation Technique Utilizing Diffusion from Implanted Polysilicon Layer,” IEEE Electron Devices Letters, 10 pp. 319 – 321, July 1989.*
  11. O, K. K., H.-S. Lee, and L. R. Reif, “A BiCMOS Process Utilizing Selective Epitaxy for Analog/Digital Applications,” IEEE Trans. Electron Devices, 36 pp. 1362 – 1369, July 1989.*
  12. O, K. K., L. R. Reif, and H.-S. Lee,” BiCMOS Transistors:  Merged Bipolar/Sidewall MOS Transistors,” IEEE Electron Device Letters, 10 pp. 517 – 519, Nov. 1989.*
  13. Huang, J., R. T. Howe, and H.-S. Lee, “Vacuum-Insulated Field-Effect Transistor” Electronics Letters, vol. 25, pp. 1571-1573, 1989.*
  14. Ware, K. M., H.-S. Lee, and C. G. Sodini,” A 200 MHz CMOS Phase-Locked-Loop with Dual Phase Detectors,” IEEE J. Solid State Circuits, SC-24, pp. 1560 – 1568, Dec., 1989.*
  15. K. K. O, L. R. Reif, and H.-S. Lee, “PMOS Input Merged Bipolar/Sidewall MOS Transistors (PBiMOS Transistors), Electron Device Letters, Vol. 12, No. 2, pp. 68-70, February, 1991.*
  16. Karanicolas, A. N., K. K. O., J. Y. Wang, H.-S. Lee, and L. R. Reif, “A High Frequency Fully Differential BiCMOS Operational Amplifier”,  IEEE Journal of Solid-State Circuits, SC-26, pp. 203-208,  March 1991.*
  17. J. Kung, A. Karanicolas, and H.-S. Lee, “A Compact, Inexpensive Apparatus for One-Sided Etching in KOH and HF”, Sensors and Actuators Physical, Volume 19, No. 3, pp. 209-215.*
  18. P. Yu, S. Decker, H.-S. Lee, C. Sodini, and J. Wyatt Jr., “CMOS Resistive Fuse Circuits for Image Smoothing and Segmentation,” IEEE Journal of Solid-State Circuits, SC-27, pp. 545-553, April, 1992.*
  19. J.L. Wyatt, Jr., C. Keast, M. Seidel, D. Standley, B. Horn, T. Knight, C.G. Sodini, H.-S. Lee, and T. Poggio, “Analog VLSI Systems for Image Acquisition and Fast Early Vision
  20. Processing,”  Int’l J. of Computer Vision, vol. 3, No. 3 pp. 217-230, 1992.*
  21. O, K.K. J.L. Lutsky, L.R. Reif, and H.-S. Lee, “An NMOS Input Merged Bipolar/Sidewall-MOS Transistor with a Bypass Sidewall MOS Transistor (NBiBMOS),” IEEE Electron Device Letters, vol. EDL-13, pp. 563-565, November, 1992.*
  22. Kung, J. T. and H.-S. Lee, “An Integrated Air-Gap-Capacitor Pressure Sensor and Digital Readout with Sub-100 Attofarad Resolution”,  IEEE/ASME J. Microelectromechanical Systems, January 1993.* 
  23. Hakkarainen, J. M. and H.-S. Lee, “A 40 x 40 CCD/CMOS AVD Processor for Use in a Stereo Vision System,”  IEEE J. Solid-State Circuits, SC-28, pp. 799-807, July, 1993.*
  24. Kung, J.T., R. Mills, and H.-S. Lee, “Digital Cancellations of Noise and Offset for Capacitive Sensors,”  IEEE tans. Instrumentation and Measurements. October, 1993.*
  25. Yu, P. C. and H.-S. Lee, “A High-Swing 2V CMOS Operational Amplifier with Gain Enhancement Using a Replica Amplifier,”   IEEE J. Solid-State Circuits, vol. SC-28, pp. 1265-1272, Dec. 1993.*
  26. Karanicolas, A. N., H.-S. Lee, and K. Bacrania, “A 15b 1 Ms/s Digitally Self-Calibrated Pipeline ADC,”  IEEE J. Solid-State Circuits,  vol. SC-28, pp. 1207-1215, Dec. 1993.*
  27. Tewksbury, T. L. and H.-S. Lee, “Characterization Modeling and Minimization of Transient Threshold Voltage Shifts in MOSFETs,” IEEE J. Solid-State Circuits, vol. SC-29, pp. 239-252, March, 1994.*
  28. Lloyd, J., and H.-S. Lee, “A CMOS Op Amp with Fully-Differential Gain-Enhancement,” IEEE trans. Circuits and Systems, vol. CAS-41, pp. 241-242, March 1994*
  29. Lee, H.-S., “A 12-bit 600kS/s Digitally Self-Calibrated Pipeline Algorithmic ADC,” IEEE J. Solid-State Circuits, vol. SC-29, pp. 509-515, April, 1994.
  30. Thompson, B., H.-S. Lee, and L. DeVito, “A 300 MHz BiCMOS Serial Data Transceiver,”  IEEE J. Solid-State Circuits, *
  31. Nadeem, S., C.G. Sodini, and H.-S. Lee, “16-Channel Oversampled Analog-to-Digital Converter for Multi-Channel Applications,”  IEEE J. Solid-State Circuits. vol. SC-29, pp. 1077-1085, September, 1994.*
  32. Yu, P. C. and H.-S. Lee, “Settling Time Analysis of a Replica Amp Gain Enhanced Operational Amplifier,”  IEEE Trans. Circuits & Sys.II, vol. 42, pp 137-142, March, 1995.*
  33. Bulzacchelli, J. F.,  H.-S. Lee, K. G. Stawiasz, S. Alexandrou, and M. B. Ketchen, “Picosecond Optoelectronic Study of Superconducting Microstrip Lines,” IEEE Transactions on Applied Superconductivity, Vol. 5, No. 2, pp. 2839-2843, June 1995.*
  34. Yu, P. C. and H.-S. Lee, “A Pipeline A/D Conversion Technique with Near-Inherent Monotonicity,”  IEEE Trans. Circuits & Sys.II, vol. 42, pp 500-502, July, 1995.*
  35. Paul, S. A. and H.-S. Lee, “A 9b Charge-to-Digital Converter for Integrated  Image Sensors,” IEEE Journal of Solid-State Circuits vol. SC-31,  pp 1931-1938, Dec. 1996.*
  36. Yu, P. C. and H.-S. Lee, “A 2.5V 12b 5MSamples/s Pipelined CMOS ADC,”  IEEE Journal of Solid-State Circuits vol. SC-31,  pp 1854-1861, Dec. 1996.*
  37. J. F. Bulzacchelli, H.-S. Lee, S. Alexandrou, J. A. Misewich, and M. B. Ketchen, “Optoelectronic Clocking System for Testing RSFQ Circuits up to 20 GHz,”  IEEE Transactions on Applied Superconductivity, 1997*
  38.  McQuirk, I., H.-S. Lee, B.K.P. Horn, and J. L. Wyatt, Jr., “Estimating the Focus of Expansion in Analog VLSI ,”  International Journal of Computer Vision, 1997*
  39. David A. Martin, Hae-Seung Lee, and Ichiro Masaki, “A Mixed-Signal Array Processor with Early Vision Applications,” IEEE J. Solid-State Circuits, vol. SC-33, pp. 497-502, Mar. 1998*
  40. McQuirk, I., H.-S. Lee, B.K.P. Horn, and J. L. Wyatt, Jr., “Estimating the Focus of Expansion in Analog VLSI,” International Journal of Computer Vision, 1998*
  41. A. Shabra , H.-S. Lee and L. Hernandez, “Oversampled Pipeline A/D Converters with Mismatch Shaping,” Electronics letters, vol. 34, No. 6, pp508-509, March 1998*
  42. K. Gulati and H.-S. Lee, “A High-Swing CMOS Telescopic Operational Amplifier,” IEEE J. Solid-State Circuits, vol. SC-33, pp. 2010-2019, Dec. 1998*
  43. S. Paul, H.-S. Lee, J. Goodrich, T. Alailima, and D. Santiago, “A Nyquist-rate Pipelined Oversampled A/D Converter,” IEEE J. Solid-State Circuits, vol. SC-34, pp.1777 – 1787 Dec. 1999*
  44. J. F. Bulzacchelli, H.-S. Lee, J. A. Misewich, and M. B. Ketchen, “Analog-to-Digital Converter Testing Method Based on Segmented Correlations,” IEEE Transactions on Applied Superconductivity, Vol. 11, pp. 275-279, March 2001.
  45. K. Gulati and H.-S. Lee, “Low Power Reconfigurable Analog-to-Digital Converter “, IEEE J. Solid-State Circuits,  vol. 36, pp 1900-1911, Dec. 2001.
  46. J. F. Bulzacchelli and H.-S. Lee, “Direct A/D Conversion of  Multi-GHz RF Signals at 42.6 GHz Sampling Rate,” KSEA Letters, Vol. 30, No. 4, pp. 69-71, April 2002.
  47. A. Shabra and H.-S. Lee, “Oversampled Pipeline A/D Converters with Mismatch Shaping,” IEEE J. Solid-State Circuits, vol. SC-37, pp. 566-578, May. 2002.
  48. S. Luschas and H.-S. Lee, “High Speed Sigma Delta Modulators with Reduced Timing Jitter Sensitivity”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, issue: 11, November 2002, pp. 712-720.
  49. J. F. Bulzacchelli, H.-S. Lee, J. A. Misewich, and M. B. Ketchen, “Superconducting Bandpass Delta-Sigma Modulator with 2.23-GHz Center Frequency and 42.6-GHz Sampling Rate,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, pp. 1695-1702, Dec. 2002.
  50. J. F. Bulzacchelli, H.-S. Lee, J. A. Misewich, and M. B. Ketchen, “Experimental Demonstration of Superconducting Bandpass Delta-Sigma Modulator,” IEEE Transactions on Applied Superconductivity
  51. Peng, M.S. ; Hae-Seung Lee, “Study of substrate noise and techniques for minimization,” Solid-State Circuits, IEEE Journal of Vol. SC-39 , pp2080-2086, 2004
  52. S. Luschas, R. Schreier, and H.-S. Lee; “Radio frequency digital-to-analog converter” IEEE Journal of Solid-State Circuits, Volume SC-39, pp1462 – 1467 Sept. 2004
  53. J. F. Bulzacchelli, H.-S. Lee, J. A. Misewich, and M. B. Ketchen, “Development of Superconducting Bandpass Delta-Sigma Analog-to-Digital Converter,” Physica C, Vol. 412-414, pp. 1539-1545, Oct. 2004
  54. Andrew Chen, A. I. Akinwande, and H. S. Lee , “A CMOS-Based Microdisplay with Calibrated Backplane”, IEEE J. Solid-State Circuits Volume SC-40,  Dec. 2005 pp. 2746 – 2755
  55. T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway*, and H.-S. Lee, “Comparator-Based Switched-Capacitor Circuits For Scaled CMOS Technologies,” IEEE J. Solid-State Circuits, vol. SC-41, pp. 2658-2668, December 2006.
  56. H.-S. Lee and C. G. Sodini, “Mixed-Signal Integrated Circuits-Digitizing the Analog World,” Proceedings of IEEE, vol. 96, pp. 323-334, Feb. 2008.
  57. Nan Sun, Hae-Seung Lee, Donhee Ham: Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching. IEEE Trans. on Circuits and Systems 55-II(9): 877-881, 2008
  58. L. Brooks and H.-S. Lee, “Background calibration of Pipelined ADCs Via Decision Boundary Gap Estimation,”, IEEE Trans. Circuits and Systems, Nov. 2008.
  59. L. Brooks and H.-S. Lee, ” A 12b, 50MS/s, Fully Differential Zero-Crossing Based ADC,” IEEE J.Solid-State Circuits, vol. SC-44, pp. 3329 – 3343, Dec. 2009.
  60. T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, “Noise Analysis for Comparator-Based Circuits,” IEEE Trans. Circuits and Systems, March, 2009.
  61. H.-S. Lee, L.G. Brooks,  and C. G. Sodini, “Zero-Crossing Based Ultra Low Power A/D Converters,” Proceedings of IEEE, vol. 98, pp. 315-332, Jan. 2010.
  62. P. Lajevardi, A. Chandrakasan, and H.-S. Lee, “Zero-Crossing Detector Based Reconfigurable Analog System,” IEEE J. Solid-State Circuits, vol. SC-46, pp2478-2487, November, 2011
  63. S. Lee,  A. Chandrakasan, and H.-S. Lee, “A Voltage Scalable Zero-Crossing Based Pipelined ADC,” IEEE J. Solid-State Circuits, vol. SC-47, pp. 1603-1614, July 2012
  64. Kailiang Chen, H.-S. Lee, A. P. Chandrakasan, and C.G. Sodini, “Ultrasonic Imaging Transceiver Design for CMUT: A Three-Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a Noise-Optimized Receiver,” IEEE J. Solid-State Circuits, vol. SC-48, pp. 2734-2745, Nov. 2013.
  65. S. Shin, J.C. Rudell, D.C. Daly, C.E. Munoz, D.Y. Chang, K. Gulati, H.-S. Lee, and M.Z. Straayer, “A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration,” IEEE J. Solid-State Circuits, vol. SC-49, pp. 1366-1382, June 2014.
  66. Sunghyuk Lee, A.P Chandrakasan, and H.-S. Lee, “A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration,” IEEE J. Solid-State Circuits, vol. SC-49, pp. 2846-2856, Dec. 2014
  67. K. Chen, C. G. Sodini, and H.-S. Lee, A Column-Row-Parallel ASIC Architecture for 3D Wearable / Portable Medical Ultrasonic Imaging, “IEEE J. Solid-State Circuits, vol. SC-51, pp. 738-751, March 2015
  68. J. Seo, S. J. Pietrangelo, H.-S. Lee, and C. G. Sodini, “Noninvasive Arterial Blood Pressure Waveform Monitoring Using Two-Element Ultrasound System,” IEEE Trans. Ultrasonics, Ferrorelectrics, and Frequency Control, vol-62, pp. 776-784, April, 2015
  69. P. Choi, S. Goswami, U. Radhakrishna,  D. Khanna, C-C Boon; H.-S. Lee, D. Antoniadis, and L-S Peh, “A 5.9-GHz Fully Integrated GaN Frontend Design With Physics-Based RF Compact Model,” IEEE Trans. Microwave Theory and Techniques, vol. 63, pp. 1163-1173, April, 2015
  70. Hyun H. Boo, Duane S. Boning, Hae-Seung Lee, “A 12b 250MS/s Pipelined ADC with Virtual Ground Reference Buffers,” in IEEE J. Solid-State Circuits, vol. SC-50, pp. 2912-2921, Dec. 2015
  71. D.-Y. Yoon, S. Ho, and H.-S. Lee, “A Continuous-Time Sturdy-MASH ΔΣ Modulator in 28nm CMOS” in IEEE J. Solid-State Circuits, vol. SC-50, pp. 2880-2890, Dec. 2015
  72. K. Chen, B.C. Lee, K. Thomenius, B. Khuri-Yakub, H.-S. Lee, and C.G. Sodini, “Over 20 dB Reduction of Tx 2nd-Order Harmonic using Interleaved Checker Board I&Q Excitation,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control
  73. P. Srivastava, S. Chung, D. Piedra, H.-S. Lee, and T. Palacios, “GaN High-Electron Mobility Transistor Track-and-Hold Sampling Circuit With Over 100-dB Signal-to-Noise Ratio,” IEEE Electron Device Letters, vol. 37, pp. 1314-1317, October, 2016

Proceedings of Refereed Conferences

  1. Lee, H.-S., D. A. Hodges, and P. R. Gray, “A Self-Calibrating 12b 12S CMOS ADC,” Digest of Technical Papers, 1984 International Solid-State Circuits Conference,  San Francisco, CA, February, 1984, pp. 64-65.*
  2. McCarroll, B. J., C. G. Sodini, and H.-S. Lee, “A High-Speed Comparator for Use in ADC,” Digest of Technical Papers, VLSI Circuits Symposium, Karuizawa, Japan, May 1987, pp. 115-16.*
  3. O., K.,  H.-S. Lee, and L. R. Reif, “2mm BiCMOS Process with Fully Optimized MOS and Bipolar Transistors,” Extended Abstracts, Electrochemical Society, Philadelphia, PA, May 1987, p. 407.*           
  4. O., K. K., H.-S. Lee and L. R. Reif, “A Bipolar Process with Semidielectric Isolation by Selective Epi Growth,” Extended Abstracts, Bipolar Technology Meeting, Minneapolis, MN, September 1988, pp. 245-248.*
  5. O., K. K.,  H.-S. Lee, L. R. Reif, and W. Frank, “A 2mm BiCMOS Process Utilizing Selective Epitaxy,” Extended Abstracts, Device Research Conference, Boulder, CO, June 1988, pp. IIIA-1; also (expanded version) Extended Abstracts, 1988 SRC Techcon, Dallas, TX, October 1988.*
  6. Ware, K. M., H.-S. Lee, and C. G. Sodini, “A 200 MHz CMOS PLL with Dual Phase Detectors,” Digest of Technical Papers 1989 IEEE International Solid-State Circuits Conference, New York, NY, February 1989, pp. 192 – 193.*
  7. K. K. O, H.-S. Lee, and L. R. Reif”, BiMOS Transistors:  Merged Bipolar/Sidewall MOS Transistors”, 47th Annual Device Research Conf., Paper IIB-8, 1989.*    
  8. Miller, G. A., M. Timko, H.-S. Lee, E. Nestler, M. Mueck, and P. Ferguson, “An 18-bit, 10msec Self-Calibrating ADC,” Digest of Technical Papers,  IEEE International Solid-State Circuits Conference, San Francisco, CA, Feb. 1990, pp. 168 – 169.
  9. Karanicolas, A. N.,  K. K. O, J. Y. Wang, H.-S. Lee, L. R. Reif, “A High Frequency Fully Differential BiCMOS Operational Amplifier,” Proceedings of the 1990  IEEE Custom Integrated Circuits Conference, Boston, MA  May 1990, pp. 8.3.1 – 8.3.4.*
  10. Kung, J. T. and H.-S. Lee, “An Integrated Air-gap Capacitor Process for Sensor Applications”, Proceedings of Transducer ’91, June 1991, San Francisco, pp. 1010 1013.*
  11. Hakkarainen, J. M., J. J. Little, H.-S. Lee, and J. L. Wyatt, Jr., “Interaction of Algorithm and Implementation for Analog VLSI Stereo Vision”, Proceedings of SPIE International Symposium on Optical Engineering and Photonics in Aerospace Sensing, Orlando, FL, April 1991, pp. 173-184.*       
  12. Lee, H.-S., and P. Yu, “CMOS Resistive Fuse Circuits”, Proceedings of IEEE 1991 Symposium on VLSI Circuits, Oiso, Japan, May 1991, pp. 109-110.*
  13. Thompson, B., and H.-S. Lee, “A BiCMOS PLL Pair for Serial Data Communication”, IEEE Custom Integrated Circuits Conference, Boston, MA, May 1992.*
  14. Wyatt, Jr., J.L., C. Keast, M. Seidel, D. Standley, B. Horn, T. Knight, C.G. Sodini, H.-S. Lee, and T. Poggio, “Analog VLSI Systems for Early Vision Processing,” to appear in Proc. 1992 IEEE Int’l. Symp. on Circuits and Systems, San Diego, CA, May 1992.*
  15. Wyatt, Jr., J.L., Jr., C. Keast, M. Seidel, D. Standley, B. Horn, T. Knight, C.G. Sodini, and H.-S. Lee, “Small, Fast Analog VLSI Systems for Early Vision Processing,” Proceedings of Intelligent Vehicles, 1992 Symposium, July 1992, pp. 69-73.*
  16. Yu, P. C. and H.-S. Lee, “A CMOS Resistive-Fuse Processor for 2-D Image Acquisition, Smoothing and Segmentation,” Proceedings of IEEE European Solid-State Circuits Conference, Copenhagen, Denmark, September 1992, pp. 147-150.*
  17. Hakkarainen, J. M. and H.-S. Lee, “A 40 x 40 CCD/CMOS AVD Processor for Use in a Stereo Vision System,” Proceedings of IEEE European Solid-State Circuits Conference, Copenhagen, Denmark, September 1992, pp. 155-158.*
  18. Yu, P. C. and H.-S. Lee, “A High-Swing 2V CMOS Operational Amplifier with Gain Enhancement Using a Replica Amplifier,” IEEE 1993 International Solid-State Circuits Conference,  Digest of Technical Papers, pp. 116-117, February 1993, San Francisco, CA.*
  19. Karanicolas, A. N., H.-S. Lee, and K. Bacrania, “A 15b 1 Ms/s Digitally Self-Calibrated Pipeline ADC,” IEEE 1993 International Solid-State Circuits Conference, Digest of Technical Papers, pp. 60-61, February 1993, San Francisco, CA.*
  20. Thompson, B., H.-S. Lee, and L. DeVito, “A 300 MHz BiCMOS Serial Data Transceiver,” Proceedings of IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1993.*
  21. Tewksbury, T. L. and H.-S. Lee, “Characterization Modeling and Minimization of Transient Threshold Voltage Shifts in MOSFETs,” Proceedings of  IEEE Custom Integrated Circuits Conference, San Diego, CA, May 1993.*
  22. Lee, H.-S., “A 12-bit 600kS/s Digitally Self-Calibrated Pipeline Algorithmic ADC,” IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 121-122, Kyoto, Japan, May, 1993.*
  23. Nadeem, S., C. G. Sodini, and H.-S. Lee, “A 1mW Delta-Sigma Modulator for Multichannel Applications,”  IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 119-120, Kyoto, Japan, May, 1993.*
  24. Lee, H.-S., A.N. Karanicolas, “Accuracy Limitation and Calibration Techniques for Pipeline A/D Converters,” (invited paper) Proceedings of1993 International Conference on VLSI and CAD, pp. 293-298, November 16, 1993, Taejon, Korea.*
  25. Bulzacchelli, J. F., H.-S. Lee, K.G. Stawiasz, and M.B. Ketchen,  “Picosecond Optoelectronic Study of Superconducting Microstrip Transmission Lines,”  Applied Superconductivity Conference, Boston, MA, October, 1994.*
  26. I. Masaki, S. Decker, A. Gupta, B.K.P. Horn, H.-S. Lee, D.A. Martin, C.G. Sodini, J.K. White, and J.L. Wyatt, Jr., “Cost-Effective Vision Systems for Intelligent Vehicles,” Proceedings of IEEE International Intelligent Vehicles Symposium, pp 39-43, Paris, France, October, 1994.
  27. Paul, S. A. and H.-S. Lee, “A 9b Charge-to-Digital Converter for Integrated  Image Sensors,” ISSCC Digest of Technical Papers,  pp 188-189, San Francisco, CA, Feb. 1996.*
  28. Yu, P. C. and H.-S. Lee, “A 2.5V 12b 5MSamples/s Pipelined CMOS ADC,”  ISSCC Digest of Technical Papers,  pp 314-315, San Francisco, CA, Feb. 1996.*
  29. Yang, J. and H-.S. Lee, “A CMOS 12-bit 4MHz A/D Converter with Commutative Feedback Capacitor,”  1996 IEEE Custom Integrated Circuits Conference, San Diego, CA,  May, 1996.*
  30. J. F. Bulzacchelli, H.-S. Lee, S. Alexandrou, J. A. Misewich, and M. B. Ketchen, “Optoelectronic Clocking System for Testing RSFQ Circuits up to 20 GHz,” Applied Superconductivity Conference, Pittsburgh, PA, August 1996).*
  31. McQuirk, I., H.-S. Lee, and B.K.P. Horn, “An Analog VLSI Chip for Estimating the Focus of Expansion,”  ISSCC Digest of Technical Papers,  pp 40-41, San Francisco, CA, Feb. 1997.*
  32. Martin, D., H-S. Lee, and I. Masaki, “A Mixed-Signal Array Processor with Early Vision Application,”  1997 IEEE Custom Integrated Circuits Conference,        San Diego, CA,  May, 1997.*
  33. J.A. Lloyd, H.-S. Lee, L. Parameswaran, M.A. Schmidt and C.G. Sodini, “An Adaptive Calibration Technique for Micromachined Pressure Sensors”, Transducers ’97, Chicago,  June, 1997.*
  34. D. A. Martin, Hae-Seung Lee, and Ichiro Masaki, “A Mixed-Signal Array Processor with ITS Applications”, IEEE ITSC, pp. 894 – 899  Nov. 1997.*
  35. K. Gulati and H.-S. Lee, “A +-2.45V Output Swing CMOS Telescopic Operational Amplifier,” Digest of Technical Papers, 1998 International Solid-State Circuits Conference, pp. 260-261, Feb. 1998, San Francisco, CA*
  36. S. Paul, H.-S. Lee, J. Goodrich, T. Alailima, and D. Santiago, “A Nyquist-rate Pipelined Oversampled A/D Converter,” Digest of Technical Papers, 1999 International Solid-State Circuits Conference, pp. 54-55, Feb. 1999, San Francisco, CA*
  37. J.F. Bulzacchelli, H.-S. Lee, J.A. Misewich, and M.B. Ketchen, “Superconducting Bandpass Delta-Sigma A/D Converter,” International Superconductive Electronics Conference, June 21-25, 1999, Berkeley, CA*
  38. J. F. Bulzacchelli, H.-S. Lee, J.A. Misewich, and M.B. Ketchen, “Analog-to-Digital Converter Testing Method Based on Segmented Correlations,” 2000 Applied Superconductivity Conference, Virginia Beach, VA,  Sept. 2000*
  39. K. Gulati and H.-S. Lee, “Low Power Reconfigurable Analog-to-Digital Converter ” accepted for publication in Digest of Technical Papers, 2001 International Solid-State Circuits Conference, Feb. 2001, San Francisco, CA*
  40. Shabra, A. and H.-S. Lee, “A 12-bit Mismatch-Shaped Pipeline A/D Converter,” in Digest of Tech. Papers, 2001 Symposium on VLSI Circuits, July 2001, pp. 211-214.
  41. J. F. Bulzacchelli, H.-S. Lee, J. A. Misewich, and M. B. Ketchen, “Superconducting Bandpass Delta-Sigma Modulator with 2.23 GHz Center Frequency and 42.6 GHz Sampling Rate,” Digest of Technical Papers, 2002 International Solid-State Circuits Conference, pp. 188-189, Feb. 2002, San Francisco, CA.
  42. S. Luschas and H.-S. Lee, “Output Impedance Specifications for High-Frequency, Narrowband Communications Digital-to-Analog Converters” International Symposium on Circuits and Systems (ISCAS) May 2003.
  43. Luschas, S. ; Schreier, R. ; Lee, H.-S., “A 942 MHz output, 17.5 MHz bandwidth, -70dBc IMD3 ΣΔ DAC,” Custom Integrated Circuits Conference, 2003. Proceedings of the IEEE 2003
  44. M. S. Peng and H.-S. Lee, “Study of Substrate Noise and Techniques for Minimization, “accepted for publication in IEEE Symposium on VLSI Circuits, June 2003
  45. Andrew Chen, A. I. Akinwande, and H. S. Lee , “A CMOS-Based Microdisplay with Calibrated Backplane”, 2005 IEEE ISSCC, Digest of Technical Papers, Feb. 2005, San Francisco, CA pp 139-140
  46. T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway and H.-S. Lee, “Comparator-based switched-capacitor circuits for scaled CMOS technologies,” in Digest of Technical Papers. ISSCC, 2006, pp. 220-221.
  47. L. Brooks and H.-S. Lee, “A Zero-crossing based 8b 200MS/s pipelined ADC,” ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2007.
  48. Albert Chow, Hae-Seung Lee: Transient Noise Analysis for Comparator-Based Switched-Capacitor Circuits. ISCAS 2007: 953-956
  49. H.-S. Lee, “Limits of Power Consumption in Analog Circuits,” (invited key note paper), Digest of Technical Papers, Symposium on VLSI Circuits, Kyoto, Japan, June 2007.
  50. Soon-Kyun Shin ; Yong-Sang You ; Seung-Hoon Lee ; Kyoung-Ho Moon ; Jae-Whui Kim ;Brooks, L. ; Hae-Seung Lee, “A fully-differential zero-crossing-based 1.2V 10b 26MS/s pipelined ADC in 65nm CMOS,” Digest of Technical Papers, Symposium on VLSI Circuits, Kyoto, Japan, June 2008
  51. Ho-Young Lee, Tae-Hwan Oh, Ho-Jin Park, Hae-Seung Lee, Mark Spaeth, Jae-Whui Kim: A 14-b 30MS/s 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration. CICC 2007: 313-316
  52. Moo-Yeol Choi, Sung-No Lee, Seung-Bin You, Wang-Seup Yeum, Ho-Jin Park, Jae-Whui Kim, Hae-Seung Lee: A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control. CICC 2008: 89-92
  53. Tae-Hwan Oh, Ho-Young Lee, Ju-Hwa Kim, Ho-Jin Park, Kyoung-Ho Moon, Jae-Whui Kim, Hae-Seung Lee: A 16b 10MS/s digitally self-calibrated ADC with time constant control. CICC 2008: 113-116
  54. A. Chow and H.-S. Lee, “Offset Cancellation for Zero Crossing Based Circuits,” IEEE ISCAS, June 2010.
  55. L. Brooks and H.-S. Lee, ” A 12b, 50MS/s, Fully Differential Zero-Crossing Based ADC without CMFB”, Digest of Technical Papers IEEE ISSCC, Feb. 2009.
  56. J. Chu, L.G. Brooks, and H.-S. Lee, “A Zero-Crossing Based 12b 100MS/s Pipelined ADC with Decision Boundary Gap Estimation Calibration,” in Digest of Technical Papers, Symposium on VLSI Circuits, Kyoto, Japan, June 2010.
  57. P. Lajevardi, A. Chandrakasan, and H.-S. Lee, “Zero-Crossing Detector Based Reconfigurable Analog System,” in Digest of Technical Papers, Asian Solid-State Circuits Conference, Beijing, China, November 2010.
  58. J. Chu and H.-S. Lee, “A 450 MS/s 10-bit time-interleaved zero-crossing based ADC,” Proceedings of the IEEE Custom Integrated Circuits Conference, Sept. 19-21, 2011, San Jose, CA
  59. S. Lee,  A. Chandrakasan, and H.-S. Lee, “A 12b 5-to-50MS/s 0.5-to-1V Voltage Scalable Zero-Crossing Based Pipelined ADC,” Proceedings of the European Solid-State Circuits Conference, pp. 355-358, Sept. 12-16, 2011, Helsinki, Finland
  60. A. Chang, H.-S. Lee and D. Boning, “Redundancy in SAR ADCs,” GLSVLSI ’11, Lausanne, Switzerland, May 2011
  61. N. Sun, H.-S. Lee, and D. Ham, “A 2.9-mW 11-b 20-MS/s pipelined ADC with dual-mode-based digital background calibration,” Proceedings of European Solid-State Circuits Conference,  Bordeaux, France, September, 2012.
  62. S. Shin, J.C. Rudell, D.C. Daly, C.E. Munoz, D.Y. Chang, K. Gulati, H.-S. Lee, and M.Z. Straayer, “A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS,” IEEE Custom Integrated Circuits Conference, San Jose, CA, September, 2012
  63. Do Yoen Yoon, Hae-Seung Lee, and Jeff Gealow, “Power Efficient Amplifier Frequency Compensation for Continuous-Time Delta-Sigma Modulators,” The IEEE 56th Int’l Midwest Symposium on Circuits & Systems Proceedings, Columbus, OH, August 2013.
  64. Albert H. Chang, Hae-Seung Lee, and Duane Boning, “A 12b 50MS/s 2.1mW SAR ADC with Redundancy and Digital Background Calibration,” Proceedings of European Solid-State Circuits Conference,  Venice, Italy, September, 2013.
  65. Sunghyuk Lee, A.P Chandrakasan, and H.-S. Lee, “A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration,” IEEE ISSCC Digest of Technical Papers, pp. 384 – 385, San Francisco, CA, Feb. 2014.
  66. Dong-Young Chang, C.  Munoz, D. Daly, S.-K. Shin,K. Guay, T. Thurston, H.-S. Lee, K. Gulati, and M. Straayer, “A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR,” IEEE ISSCC Digest of Technical Papers, pp. 204 – 205, San Francisco, CA, Feb. 2014.
  67. Pilsoon Choi, S. Goswami, C. C. Boon, L.-S. Peh, and H.-S. Lee A Fully Integrated 5.9GHz RF Frontend in 0.25μm GaN-on-SiC for Vehicle-to-Vehicle Applications,” Proceedings of 2014 RFIC, Tampa Bay, FL, June 2014.
  68. Kailiang Chen, H.-S. Lee, and C. G. Sodini, “A Column-Row-Parallel ASIC Architecture for 3D Wearable / Portable Medical Ultrasonic Imaging,” Digest of Technical Papers, 2014 Symposium on VLSI Circuits, Honolulu, HI, June 2014.
  69. Hyun H. Boo, Duane S. Boning, Hae-Seung Lee, “A 12b 250MS/s Pipelined ADC with Virtual Ground Reference Buffers,” IEEE ISSCC Digest of Technical Papers, pp. 282-283, Feb. 2015
  70. D.-Y. Yoon, S. Ho, and H.-S. Lee, “A 85dB DR, 74.6dB SNDR, 50MHz BW  CT MASH ΔΣ Modulator in 28nm CMOS” IEEE ISSCC Dig. of Tech. Papers, pp. 272-273, Feb. 2015
  71. K. Chen, B. C. Leey, K. Thomenius, B. T. Khuri-Yakuby, H.-S. Lee, and C.G. Sodini, “A Column-Row-Parallel Ultrasound Imaging Architecture for 3D Plane-wave Imaging and Tx 2nd-Order Harmonic Distortion (HD2) Reduction”” Proceedings of 2015 IEEE International Ultrasonics Symposium
  72. S. Chung and H.-S. Lee, “200 MS/s 98-dB SNRTrack-and-Holdin 0.25-um GaN HEMT,” in Proceedings of IEEE Custom Integrated Circuits Conference, Sept. 2015
  73. J. Seo, S. J. Pietrangelo, H.-S. Lee, and C. G. Sodini, “Carotid Arterial Blood Pressure Waveform Monitoring Using a Portable Ultrasound System,” Proceedings of the Annual Conference of the Engineering in Medicine and Biology Society, Milan, Italy, Sept. 2015
  74. C. G. Sodini, J. Seo, S. J. Pietrangelo, T. Heldt, E. S. Winokur, D. He, and H.-S. Lee, “Mean Arterial Blood Pressure and Pulse Pressure Wave Measurement with Low Cost Technologies,” Proceedings of the Annual Conference of the Engineering in Medicine and Biology Society, Milan, Italy, Sept. 2015
  75. D. Prashanth and H.-S. Lee, “A Sampling Clock Skew Correction Technique for Time-Interleaved SAR ADC,” in Proceedings of 2016 GLSVLSI, Boston, MA, May 2016.
  76. X. Yang and H.-S. Lee, “Design of a 4th-order Multi-stage Feedforward Operational Amplifier for Continuous-time Bandpass Delta Sigma Modulators, “ Proceeding of 2016 ISCAS, pp 1058-1061, Montreal, Canada, May 2016.
  77. D. Prashanth and H.-S. Lee, “A sampling clock skew correction technique for time-interleaved SAR ADCs,” Proceedings of the 2016 International Great Lakes Symposium on VLSI, pp 129-132, Boston, MA, May 2016.
  78. S. Pietrangelo, H.-S. Lee, and C.G. Sodini, “A Wearable Transcranial Doppler Ultrasound Phased Array System,” 16th International Symposium on Intracranial Pressure and Neuromonitoring, Cambridge, MA, June 2016
  79. D. Robertson, A. Buchwald, M. Flynn, H.-S. Lee, U-K Moon, and B. Murmann, “Data converter reflections: 19 papers from the last ten years that deserve a second look, “ Proceedings of 2016 European Solid-State Circuits Conference, pp161-164, Lausanne, Switzerland, Sept. 2016.

​Professional Magazine Articles

​Lee, H.-S, “Development of Self-Calibrating A/D Converters,” IEEE Solid-State Circuits Magazine, vol. 6, issue 2, pp.18-21, 2014